Stacking of semiconductor chips is a desirable technology for its capability of meeting the requirements in high integration and miniaturization of semiconductor packages and enhancing the ability and capacity of a single semiconductor package so as for the semiconductor package to be suitable for use in low-profile, large-capacity and high-speed electronic devices.
Referring to FIG. 1A, a conventional chip-stacking semiconductor package includes: a first semiconductor chip 11 mounted on and electrically connected to a side of a substrate 10 in a flip-chip manner; a plurality of solder balls 12 implanted to a side of the substrate 10 opposing to the side mounted with the first semiconductor chip 11 and configured to be electrically connected to an external electronic device; at least a second semiconductor chip 13 attached to the first semiconductor chip 11 and electrically connected to the substrate 10 by bonding wires 14; and an encapsulant 15 formed on the substrate 10 and encapsulating the first and second semiconductor chips 11, 13.
However, a cost issue has been raised for the above chip-stacking semiconductor package because the first and second semiconductor chips 11, 13 are electrically connected to the same said substrate 10. In such case, if one of the semiconductor chips is defective, the semiconductor package as a whole would fail. And, it only allows the yield test to be conducted on both the semiconductor chips as a whole instead of each single semiconductor chip, such that once a defect is found, the semiconductor package as a whole must be discarded. This is not cost-effective.
Referring to FIG 1B, to solve the above cost issue, another conventional semiconductor package has been developed by Package on Package (POP) technology, which comprises at least two packages 16 that are stacked and electrically connected to each other by conductive elements 17. Each of the packages 16 includes a substrate 160, a semiconductor chip 161 mounted on and electrically connected to the substrate 160 in a wire-bonded manner, and an encapsulant 162 formed on a portion of the substrate 160 and encapsulating the semiconductor chip 161. The conductive elements 17 are mounted on the substrates 160. Moreover, a plurality of solder balls 163 are implanted to a side of the substrate 160 of the underlying/lowermost package 16 as opposed to the other stack-disposed side of the substrate 160 and configured to be electrically connected to an external electronic device.
However, the POP semiconductor package has a limit in size. The height of each of the packages 16 is the sum of heights of the substrate 160 and the encapsulant 162 that encapsulates the semiconductor chip 161. With the semiconductor chip 161 being mounted on the substrate 160, the height of the encapsulant 162 must be increased. In such case, the overall height of the semiconductor package would easily exceed the expected range, and the POP semiconductor package thus fabricated is hardly compact, leading to its limited applicability in electronic devices. Another issue is overheating. With the semiconductor chip 161 being encapsulated by the encapsulant 162, heat generated by the semiconductor chip 161 in operation is accumulated rather than efficiently dissipated, and in consequence the semiconductor chip 161 is likely to be overheated and damaged.
Therefore, it is important and urgent to solve the above problems encountered in the conventional semiconductor packages.